One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to generally as chemical vapor deposition (“CVD”). Conventional thermal CVD processes supply reactive gases to the substrate surface, where heat-induced chemical reactions take place to produce a desired film. Plasma enhanced CVD techniques, on the other hand, promote excitation and/or dissociation of the reactant gases by the application of radio frequency (RF) or microwave energy. The high reactivity of the released species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such plasma processes.
As semiconductor device sizes have become smaller and integration density increases, many issues have become of increasing concern to semiconductor manufacturers. One such issue is that of interlevel “crosstalk.” Crosstalk is the undesired coupling of an electrical signal on one metal layer onto another metal layer, and arises when two or more layers of metal with intervening insulating or dielectric layers are formed on a substrate. Crosstalk can be *reduced by moving the metal layers further apart, minimizing the areas of overlapping metal between metal layers, reducing the dielectric constant of the material between metal layers and combinations of these and other methods. Undesired coupling of electrical signals can also occur between adjacent conductive traces, or lines, within a conductive layer. As device geometries shrink, the conductive lines become closer together and it becomes more important to better isolate them from each other.
Another such issue is the “RC time constant” of a particular trace. Each conductive trace has a resistance, R, that is a product of its cross section and bulk resistivity, among other factors, and a capacitance, C, that is a product of the surface area of the trace and the dielectric constant of the material or the space surrounding the trace, among other factors. If a voltage is applied to one end of the conductive trace, charge does not immediately build up on the trace because of the RC time constant. Similarly, if a voltage is removed from a trace, the trace does not immediately drain to zero. Thus high RC time constants can slow down the operation of a circuit. Unfortunately, shrinking circuit geometries produce narrower traces, which results in higher resistivity. Therefore it is important to reduce the capacitance of the trace, such as by reducing the dielectric constant of the surrounding material between traces, to maintain or reduce the RC time constant.
In order to further reduce the size of devices on integrated circuits, it has become necessary to use insulators that have a lower dielectric constant than the insulators of previous generations of integrated circuits. To this end, semiconductor manufacturers, materials suppliers and research organizations among others have been researching and developing materials for use as intermetal dielectric (IMD) layers in integrated circuits that have a dielectric constant (k) below that of undoped silicon oxide (USG, generally between about 3.9-4.2) and below that of fluorine-doped silicate glass (FSG, generally between about 3.4-3.7).
One such insulating material comprises silicon, oxygen and carbon and is sometimes referred to as a carbon-doped silica glass or an SiOC film. A variety of different well-known techniques can be used to deposit carbon-doped silica glass insulation layers on a substrate. Such techniques include both thermal and plasma-enhanced CVD techniques. For example, one method of forming a carbon-doped silica glass film forms a plasma from a process gas comprising an oxygen-containing organosilicon compound, such as octamethylcyclotetrasiloxane (OMCTS), a carrier gas, such as helium, and another oxygen source, such as molecular oxygen.
Another exemplary method of forming a carbon-doped silica glass film forms a plasma from a process gas comprising an oxygen-free organosilicon compound, such as trimethylsilane (TMS), a carrier gas, such as helium, and an oxygen source, such as molecular oxygen. Still another method of forming a carbon-doped silica glass film forms gas phase reactions at the surface of a substrate by reacting an organosiline precursor having at least one Si—C bond, such as trimethylsilane (TMS) with ozone within a subatmospheric pressure range (e.g., between 50 Torr and below about 450 Torr) and a relatively low temperature (e.g., below 250° C.). Such methods may also employ a inert gas flow, such as a flow of helium, to stabilize the process and improve deposition uniformity.
After a carbon-doped silica glass film is formed on a substrate, it is sometimes useful to improve the mechanical, physical and/or electrical properties of the initially deposited film. One method of doing such is to subject the deposited film to a thermal cure or anneal step. There is a trend in the semiconductor industry, however, to reduce the total thermal budget that a particular wafer is exposed to during all the various steps associated with forming integrated circuits on the wafer. Reducing the overall thermal budget may include reducing either or both the peak process temperature of any given step and/or the total process time the substrate is heated at temperature.
One technique that has been developed to modify the mechanical, physical and/or electrical properties of carbon-coped silica glass films includes exposing the films to a beam of electrons as described in U.S. Pat. No. 6,582,777 assigned to Applied Materials, the assignee of the present invention.
While the electron beam modification technique described in the U.S. Pat. No. 6,582,777 is highly beneficial for a variety of applications, improved or alternative techniques for modifying the mechanical, physical and/or electrical properties of carbon-doped silica glass films are continuously being sought.